Western Digital today announced that it has kicked off production of the industry’s densest 3D NAND flash chips, which stack 64 layers atop another and enable three bits of data to be stored in each cell.
The 3D NAND flash chips are based on a vertical stacking or 3D technology that Western Digital and partner Toshiba call BiCS (Bit Cost Scaling). WD has launched its pilot production of its first 512 gigabit (Gb) 3D NAND chip based on the 64-layer NAND flash technology.
The industry’s densest 3D NAND flash chips are based on a vertical stacking or 3D technology that Western Digital and partner Toshiba call BiCS (Bit Cost Scaling). Their latest memory stores three bits of data per cell and stacks those cells 64 layers high.
In the same way a skyscraper allows for greater density in a smaller footprint, stacking NAND flash cells — versus planar or 2D memory -enables manufacturers to increase density, which enables lower cost per gigabyte of capacity. The technology also increases data reliability and improves the speed of solid-state memory.
Three-dimensional NAND has allowed manufacturers to overcome physical limitations of NAND flash as transistor sizes approached 10 nanometers and the ability to shrink them further quickly dissipated.
The latest 3D NAND chips have been used to create gum stick-sized SSDs with more than 3.3TB of storage and standard 2.5-inch SSDs with more than 10TB of capacity.
Samsung became the first company to announce it was mass-producing 3D flash chips in 2014. Their technology, called V-NAND, originally stacked 32-layers of NAND flash. Samsung’s V-NAND also crammed 3-bits per cell in what the industry refers to as triple-level cell (TLC) NAND or multi-level cell (MLC) NAND. Because Samsung uses TLC memory, its chips were able to store as much as Toshiba’s original 48-layer 3D NAND chips, which stored 128Gbits or 16GB.
Intel and Micron also produce 3D NAND.
This shows one method of achieving 3D NAND. Horizontally stacked word lines around a central memory hole provide the stacked NAND bits. The circular hole minimizes neighboring bit disturb and overall density is substantially increased.
WD first introduced initial capacities of the world’s first 64-layer 3D NAND technology in July 2016.
Pilot production of WD’s new 64-layer 3D NAND chips began in its Yokkaichi, Japan fabrication plant, and the company plans to begin mass production in the second half of 2017.
“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” Dr. Siva Sivaram, executive vice president of memory technology for WD, said in a statement.
This story, “Western Digital begins production of the world’s tallest 3D NAND ‘skyscraper'” was originally published by Computerworld.